Efficiency of Adiabatic Logic for Low-Power VLSI Using Cascaded ECRL And PFAL Inverter
نویسندگان
چکیده
The energy stored at the output can be retrieved by the reversing the current source direction discharging process instead of dissipation in NMOS network. Hence adiabatic switching offers the less energy dissipation in PMOS network and reuse the stored energy in the output capacitance by reversing the current source direction. There are the many adiabatic logic design technique are given in Literature but here two of them are chosen ECRL and PFAL, which shows the good improvement in energy dissipation and are mostly used as reference in new logic families for less energy dissipation reduction of area & power factors the simulations were done using micro wind & DSCH results.
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